Readers' comments (9)
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Posted by Mr. Alexander Teterkin on 7 September 2010 at 4:57 Hello! There is a mistake in the table 2-1 on page 31. It says that POWER7 has 2GB of L2 cache memory per chip. It should be 2MB. All the rivals are crying now, as we say in Russia! ;-) |
Posted by Scott Vetter on 8 September 2010 at 10:24 Mmm.. thought this was fixed. You are correct. It is 2MB. |
Posted by Scott Vetter on 8 September 2010 at 10:46 An update will be online within 48 hours |
Posted by Richard Bramwell on 16 February 2011 at 5:19 There are a couple of entries for "enclusure" - I suspect it should be enclosure unless we need a "clue" to find space. |
Posted by Scott Vetter on 17 February 2011 at 11:48 Thanks! I've located and corrected the two errors and they will be online the next time the papers are revised. |
Posted by Simon Marchese on 12 October 2011 at 7:27 p65 of the PDF has a table with "Internal GX Bus 1&2 19.712 Gbps" - should that not be GBPs or GiBps? See Pat O'Rourke at https://www-03.ibm.com/LotusQuickr/power7champion/Main.nsf/54ABCBBAEEB9929805256708001671F3/F5909D18ED8B220D872576E300583B20/?OpenDocument |
Posted by Mr. Scott Vetter on 16 March 2012 at 10:49 Looks like we lost our caps lock. Yes, the duplex rate is approx. 20 GBps (bytes). |
Posted by Mr. Nikolay Tikhonovetskiy on 20 March 2012 at 13:54 it's wrong file (old version). I'm waiting new draft. |
Posted by Mr. Scott Vetter on 21 March 2012 at 16:10 Mr. Tikhonoversky, are you looking for REDP-4798? |