A note about Hypervisor and the High Performance Switch.
For related information about this topic, refer to the following IBM Redbooks publication:
An Introduction to the New IBM eServer pSeries High Performance Switch, SG24-6978-00
The Hypervisor is the glue that holds all of the High Performance Switch components together. It exists within the CEC as Licensed Internal Code and is part of the firmware image. When in LPAR Ready mode, Hypervisor owns all system resources and provides an abstraction layer through which device access and control is arbitrated. It is because of these functions that Hypervisor was chosen to handle the HPS.
The HPS was originally intended to be a NUMA fast-cache adapter. To do this, it had to be available prior to system boot. This required much of the switch chip functionality to become part of system firmware, and only Hypervisor had the necessary hooks to provide abstraction of system resources. While the NUMA on POWER4 plans have been dropped, the HPS design has been continued. There is insufficient room in switch microcode to offload these functions from Hypervisor, and as such, the HPS requires the CEC to be in LPAR Ready mode.
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